1. Field of the Invention
This invention relates generally to a phase-locked loop (PLL), and more particularly to a phase-locked loop runaway detector.
2. Description of the Related Art
A phase-locked lop (PLL) is a closed-loop feedback control system that generates and outputs a signal in relation to the frequency and phase of an input signal. The PLL responds to both the frequency and phase of the input signal and automatically raises or lowers the frequency of a controlled oscillator until it matches the input signal in both frequency and phase.
FIG. 1 illustrates a block diagram of a known phase-locked loop (PLL). The PLL in FIG. 1 includes a phase-frequency detector (PFD) 110, a charge pump 125, a loop filter 130, a voltage controlled oscillator (VCO) 140, and a divider 145. The PFD 110 receives an input clock CK 1 105 and a feedback signal CKF 155 from the divider 145. The PFD 110 will output either an UP 115 or a DOWN 120 signal to the charge pump 125 depending on the difference in frequency between the input clock CKI 105 and the feedback signal CKF 155. Based on the UP 115 or DOWN 120 signal provided to the charge pump 125, the charge pump 125 outputs a charge pump voltage signal VCP 160 to the loop filter 130. The loop filter 130 may filter the charge pump voltage signal VCP 160 to eliminate noise or distortion before passing the control voltage signal VDTRL 135 to the VCO 140. Based on the control voltage signal VCTRL 135, the VCO 140 may increase or decrease the frequency of the VCO output 150.
The PLL generally operates in a steady-state (locked) or transient (unlocked) condition. When the PLL is in steady-state operation (i.e. locked), the output of the VCO 140, identified in FIG. 1 as the PLL output clock CKO 150, has a frequency N times higher than the frequency of the input, or reference, clock CKI 105. The multiple N is the divisor of the divider 145. Thus, in lock, the feedback signal CKF 155 input to the PFD 110 from the divider 145 should have exactly the same frequency as the input clock CKI 105.
Generally, the PLL may be in a transient state (i.e. unlocked) when the PLL is powering up and beginning to become locked. The PLL also may operate in a transient state if a disturbance, such as a supply glitch or other nose, causes the PLL to lose lock. In an unlocked state, the PLL output clock CKO 150 may have any value, either above or below the PLL lock frequency. To attempt to bring the PLL into a locked state, the PLL may change the VCO output frequency in a direction that will bring the PLL into lock. However, if the VCO output frequency is so high that the divider 145 fails to respond to it correctly, the PLL loop will malfunction, and the divider 145 will output either a corrupted signal or no signal at all. In this situation, the PFD 110 may see signal transitions at the CKI 105 input, but few or no transitions at the input CKF 155 from the divider 145. The PFD 110 may mistakenly interpret this situation to be one in which the VCO output frequency is too low instead of too high. Consequently, instead of activating the DOWN 120 signal to the charge pump 125 to decrease the VCO frequency, the PFD 110 may actually activate the UP 115 signal to the charge pump 125, causing the VCO frequency to increase further until it plateaus at the maximum possible operating frequency. This phenomenon, in which the VCO frequency increases unrestrained to its maximum possible value, is referred to as runaway.
Therefore, it would be desirable to have an apparatus that can detect a PLL runaway condition and force the PLL to return to a locked state.